New LSI Chip for Multiple Input Multiple Output (MIMO)

NTT DOCOMO has successfully developed a trial Large Scale Integration (LSI) chip that consumes less than 0.04 W of power yet supports Multiple-Input Multiple-Output (MIMO) signal detection and decoding for downlink transmissions at 100 Mbps, the speed required for forthcoming mobile system known as super 3G or LTE, approved by 3rd Generation Partnership Project (3GPP). Compared with chips currently used in handsets compatible with the company's High Speed Downlink Packet Access (HSDPA) service. Which have a maximum downlink rate of 75 Mbps, the new chip will enable downlinks that are more than ten times as fast.

The new chip demodulates OFDM signals transmitted in the 20 Mhz bandwidth from two antennas and detect MIMO signals based on Maximum Likelihood Detection (MLD) technology, which ensure relatively higj quality communication even in bad environments for signal reception. The chip also include error correction decoding, which requires almost the same level of complexity as MIMO signal detection. In then new chip, which is made with 65 nanometer processing, the circuit have been further optimized, particularly by eliminating redundant circuits for computationally complex processes such as MIMO-signal detection and error correction detection.